The low channel mobility in 4H-SiC power vertical MOOSFETs is a critical weakness in SiC power electronics. Achieving higher channel mobility is therefore extremely desirable, and this for several reasons:
- It allows a further lowering of the device on-resistance leading to smaller chip size (lower channel width) as well as to lower fabrication costs
- It allows device operation at oxide fields lower than 4 MV/cm, leading to increased oxide stability and reliability especially at higher temperature
- It allows a working threshold voltage of about 5V, which is required to ensure normally-off operation and adequate noise-immunity, especially in high temperature and high noise environmeOverall, SiC-based MOSFETs with sufficiently high mobility will help to build more energy efficient HVDC power energy transmissions or more energy efficient power converters in automotive applications and, most important, to reduce CO2 emission.
The key element to deal with the above issues is to understand and to engineer the gate-oxide/4H-SiC interface. Up to the beginning of the project, it was assumed that carbon clusters at the interface were responsible for the channel mobility degradation. From the results of the applied physical characterization methods used in our work, this can be definitely excluded. In parallel, a comprehensive methodology based on the combination of physical/electrical characterization together with the simulation of the electrical behavior of 4H-SiC MOSFETs was developed by the MobiSiC consortium of Fraunhofer IISB and LAAS-CNRS which allowed a significant improvement in mobility values of the demonstrator device. The advanced MOSFET device of this work shows a distinct boost in channel mobility with stable threshold voltages, significantly lower leakage currents during electrical stress, and advanced gate oxide reliabilities.
To achieve also the long-term objectives of MobiSiC, namely the formation of a research alliance between IISB and LAAS/CEMES, and also in order to facilitate the development and take-up of wide-bandgap semiconductor technology, the Fraunhofer IISB, the CNRS-LAAS, and their associates, the Chair of Electron Devices of the University Erlangen-Nuremberg and the CNRS institute CEMES recently formed the Wide Bandgap Semiconductor Alliance (WISEA). The objective of WISEA is to expand the competence of the partners in wide bandgap semiconductor processing from epitaxy and front-end processing to packaging, including state-of-the-art characterization and simulation. The WISEA facilities are available for contract research as well as for third party- funded collaborative projects.
To boost the performance of the demonstrator MOSFET optimized process parameter sets for high temperature manufacturing steps, like thermal oxidation, implantation activation anneal, and contact formation were applied. Above all, the ascertained dependence of the channel electron mobility on the 4H-SiC doping within the channel region, determined by physical and electrical characterization and modelled by simulation, has been subsequently exploited so as to achieve a significant increase of the electron mobility in MOSFET n-channels.
Project duration: September 2010 to January 2014