Publications of Fraunhofer IISB

J. Friedrich, G. Müller
Erlangen – An Important Center of Crystal Growth and Epitaxy: Major Scientific Results and Technological Solutions of the Last Four Decades
Crystal Research and Technology 55 (2020) page 1900053

The paper is among the 10 most downloaded Wiley articles published between January 1, 2019 and December 31, 2020.

It describes the historic development of the Erlangen Crystal Growth Laboratory CGL, along with the essential developments and scientific achievements in the various fields of crystal growth and epitaxy. The CGL was founded by Prof. Georg Müller in 1974 at the Department of Material Science of the University of Erlangen-Nürnberg. Later, it became today's Materials Department of Fraunhofer IISB.

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S. Besendörfer, E. Meissner, F. Medjdoub, J. Derluyn, J. Friedrich, T. Erlbacher
The Impact of Dislocations on AlGaN-GaN Schottky Diodes on Gate Failure of High Electron Mobility Transistors
Scientific Reports 10 (2020) 17252

The paper was published in the renowned Scientific Reports of the Nature Publishing Group

GaN epitaxially grown on Si is a material for power electronics that intrinsically shows a high density of dislocations. In the paper, it is shown by conductive atomic force microscopy (C-AFM) and defect selective etching that even for materials with similar total dislocation densities substantially different subsets of dislocations with screw component act as current leakage paths within the AlGaN barrier under forward bias. For AlGaN-GaN Schottky diodes, innovative methods are used to study the influence of these dislocations on the forward characteristics as well as on the breakdown behavior under high reverse bias.

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J. Erlekampf, B. Kallinger, J. Weiße, M. Rommel, P. Berwian, J. Friedrich, T. Erlbacher
Deeper Insight into Lifetime-engineering in 4H-SiC by Ion Implantation
Journal of Applied Physics 126 (2019) 045701

Title page article, issue of July 28, 2019, Journal of Applied Physics

Lifetime-engineering in 4H-SiC is important to obtain a low forward voltage drop in bipolar devices with high blocking voltages. Implantation of carbon and subsequent annealing allows one to increase the minority carrier lifetime of epitaxial layers due to annihilation of carbon vacancies and, therefore, to reduce the lifetime limiting defect 𝑍1/2. In the paper, the impact of ion implantation of other ions (N, Al, B, and As) besides carbon on minority carrier lifetime and point defect concentration is studied. The authors present a model for detailed understanding of lifetime-engineering by ion implantation. With this understanding, it was possible to reduce the detrimental 𝑍1/2 defect in thick epitaxial layers with conventional shallow ion implantation and high temperature annealing and, therefore, to enhance minority carrier lifetimes.

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Beyond SiC Power Devices and Technology - Novel High Temperature SiC CMOS 1 Micron Technology
Plenary Talk by T. Erlbacher at the 4th International Symposium on SiC Materials and Devices, December 2020, Busan, Republic of Korea

In the presentation, the benefits of SiC technology beyond discrete power devices are discussed. It is explained how SiC devices can be used in circuits for harsh environments. The required technology and design aspects are presented. Examples are shown for temperature-sensing circuits, operational amplifiers, smart power ICs, and integrated SiC gate drivers for power electronics. An outlook to SiC for quantum electronics at room temperature is given.

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J. Förthner
Lateral and Vertical Charge Compensation Structures in 4H Silicon Carbide
PhD thesis, Universität Erlangen-Nürnberg, 2020 (in German)

The PhD thesis was awarded a prize of the STAEDTLER Stiftung in October 2021.

The purpose of this work was the improvement of charge compensation structures in 4H silicon carbide, such as vertical super-junction or lateral RESURF structures. Lateral RESURF LDMOS transistors were developed for an application in integrated circuits. This transistor type provides a high blocking voltage, due to an implanted nitrogen layer with the functionality of a compensation layer to the p-type epitaxial layer. Different design parameters were investigated. A comparison between TCAD simulations and measured data of different models regarding the dimensions of the LDMOS transistor was carried out. Hereby, design rules for the best electrical behavior of the transistors were derived.

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S. Ehrlich, H. Rossmanith, M. Sauer, C. Joffe, M. März
Fast Numerical Power Loss Calculation for High-Frequency Litz Wires
IEEE Transactions on Power Electronics 36 (2021) page 2018

The paper received a 2021 IEEE Transactions on Power Electronics First Place Prize Paper Award.

It presents a fast numerical calculation method of realistic power losses for high-frequency litz wires. Explicitly, the imperfect structure of litz wires is considered when calculating losses due to an excitation current (skin losses) and external magnetic fields (proximity losses). Calculations of complex litz wires were performed and have been validated by measurements. In the calculation, the impact of the bundle structure on skin and proximity losses is examined. The method allows one to select a suitable litz wire for a specific application or to design a litz wire considering realistic twisting structures.

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A. Erdmann
Optical and EUV Lithography - A Modeling Perspective
SPIE, 2021

The book by A. Erdmann, group manager at Fraunhofer IISB and renowned expert for lithography and optics, is intended to introduce students with backgrounds in physics, optics, computational engineering, mathematics, chemistry, material science, nanotechnology, and other areas to the fascinating field of lithographic techniques for nanofabrication. It is also suitable for helping senior engineers and managers expand their knowledge of alternative methods and applications. The material for the book was compiled during many years of lecturing on optical lithography technology, physical effects, and modeling at the Universität Erlangen-Nürnberg, as well as in preparation for dedicated courses on special aspects of lithography.

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