GaN & AlN

We develop the HVPE growth of GaN bulk crystals up to 4“ diameter. The process is optimized towards a high uniform V/III ratio along the growing interface by comparing in-situ process data, ex-situ determined properties of the crystal with results from numerical modeling of the growth process. We pioneer the PVT growth of AlN crystals by using our unique N-face technology. The focus is on deeper understanding of growth mechanisms and upscaling towards 2” diameter. In our wafering line we explore advanced GaN and AlN crystal preparation technologies for epi-ready wafers. These wafers are used in our R&D clean room line to process prototype devices for fast feedback on material quality.

© Fraunhofer IISB
XRT image of HVPE GaN sample
© Anja Grabinger / Fraunhofer IISB
AlN Crystal
© Fraunhofer IISB
AlN wafer



  • Growth of GaN and AlN crystals
  • Epitaxy of AlGaN on GaN, AlN and sapphire substrates up to 4” diameter
  • Simulation of heat and mass transport of the HVPE and PVT process
  • Identification of device critical defects in nitrides
  • Characterization of crystals and epitaxial structures
    • imaging of extended defects by x-ray  topography
    • defect selective etching
    • Cathodoluminescence
    • Photoluminescence
    • Raman- and FTIR spectroscopy
  • Investigation of electrical properties of extended defects by conductive atomic force microscopy and electron beam induced current measurements and imaging techniques
© Fraunhofer IISB
Mounting of a GaN sample in a special furnace for defect selective etching
© Fraunhofer IISB
Fraunhofer IISB is equipped with a wafering laboratory for cutting GaN & AlN crystals into wafers.
© Fraunhofer IISB
The epi ready quality of GaN & AlN wafers after grinding, polishing and cleaning is controlled in house by AlGaN epitaxy up to 1450°C.

YESvGaN – GaN Vertical Power Transistors at Silicon Cost

YESvGaN targets a new low-cost wide-bandgap (WBG) power transistor technology for enabling high-efficiency power electronic systems for electromobility, industrial drives, renewable energies, and data centers.

The main objective of the project is to demonstrate innovative vertical gallium nitride (GaN) power transistors fabricated on a low-cost substrate such as silicon. This so-called vertical membrane architecture combines the superior performance of GaN as WBG power transistor material with the advantages of a vertical architecture regarding current and voltage robustness at a price competitive to silicon IGBTs. Within YESvGaN, the entire value chain is addressed – from substrate, epitaxy, process, and interconnect technology to applications in power electronic systems. The YESvGaN consortium combines the experience and competence of 23 industrial and research partners from 7 European countries.

Fraunhofer IISB contributes to the project along the entire value chain, including:

  • Analysis of epitaxial layer stacks and crystal defects, development of innovative routines for measuring the electrical properties of defects and thin membranes
  • Definition of new processes for handling of thin membranes during packaging and ceramic embedding
  • Electrical characterization of novel power devices, development of an electrical simulation model, and design of a half-bridge power module

YESvGaN Homepage

Innovative Reliable Nitride based Power Devices and Applications

Fraunhofer IISB is partner in the large highly visible EU research initiative "InRel-Power"

Focus Areas

Explore the areas of semiconductor crystal growth, epitaxy, and device processing including characterization and modeling.