Silicon Carbide

We develop the SiC epitaxy process with emphasis on improved material quality.

State of the art metrology tools such as UV-PL or XRT together with the possibility to process complete devices allows us to correlate the properties of the epilayer and the substrate with electrical device parameters. Based on the findings solutions are demonstrated how to overcome harmful defects.

In addition, the potential of SiC & diamond for quantum applications is explored. In this area, we investigate especially how color centers in SiC & diamond can be generated.


© Fraunhofer IISB
Various dislocations in SiC visualized by DSE
© Anja Grabinger / Fraunhofer IISB
In house processed SiC power devices
© Fraunhofer IISB
Lifetime map of SiC epilayer


  • n- and p-type service epitaxy on 4H-SiC wafers (up to 200mm)
  • Processing of complete SiC prototype devices (e.g. JBS, VDMOS, diodes, CMOS)
  • Correlation of material defects with device performance and reliability along the whole device processing chain
  • Characterization (imaging of structural defects by x-ray topography, and combined optical surface and photoluminescence imaging, defect selective etching, carrier lifetime measurements, deep level transient spectroscopy (DLTS), mCV and FTIR measurements)
  • Simulation of heat and mass transport for SiC epitaxy, and other high temperature SiC specific processes
© Intego GmbH / Fraunhofer IISB
Operator loading a 100 mm SiC epiwafer in a defect luminescence scanner at Fraunhofer IISB.
© Kurt Fuchs / Fraunhofer IISB
Analysis of electrical properties of SiC substrates by carrier lifetime measurements, deep level transient spectroscopy (DLTS).
© Kurt Fuchs / Fraunhofer IISB
Full wafer scale images of structural defects in various substrates up to 300mm diameter by x-ray topography.

Individual SiC Services




Focus Areas

Explore the areas of semiconductor crystal growth, epitaxy, and device processing including characterization and modeling.